In the aforementioned patent, an output of a local oscillator of a receiver is synchronized to received bits of a digital bit stream by sampling the binary value of each of the received bits several times during each of the received bits to derive for each received bit a several bit binary word representing the sampled values. These operations are performed by supplying a baseband output of the receiver to a hard limiter, which in turn drives a data input of a shift register, having a shift input responsive to a variable frequency output of a counter responsive to a crystal oscillator. An addressable memory is addressed in response to the several bit binary word. The memory derives a control signal having a value determined by estimates of the noise of each received bit of the digital bit stream and the relative phase difference between the digital bit stream and the local oscillator, as indicated by the number and positions of binary bit transitions in the several bit binary word of the shift register output. The control signal derived by the addressable memory is supplied to an averaging, i.e., low pass filter, that is enabled in synchronism with each derivation of a control signal by the addressable memory. The output of the averaging filter is continuously supplied to a controller for the counter. It has been found that this continuous control of the counter has a tendency to cause time base jitter of the sampling operation. Jitter has been found to occur even though there is substantial low pass filtering of the control signal supplied by the addressable memory to the counter, which controls the data bit sampling frequency.
In the preferred embodiment of the aforementioned patent, the addressable memory derives, from each addressed output thereof, an eight bit signal. Three of the bits control the effective rate at which data are shifted to and in the shift register and therefore the sampling rate of data bits supplied to the receiver, i.e., the local oscillator frequency. One of the memory output bits indicates the binary value of the data bit which caused the memory to be addressed. Two of the bits indicate the quality of the data bit, while one of the bits indicates if the bit should be erased. One bit at each address also indicates whether the receiver appears to be in synchronism with the received data bit stream.
The output bits at each address of the memory are pre-programmed as a function of the various combinations of samples supplied as address inputs to the memory by the shift register. Estimates of the amount of noise in a received data bit are based on the number of transitions in the sampled values supplied by the shift register to the memory address input. The noise estimate controls the values of the quality, eraser and sync indicator bits, as well as the amount of correction to be applied to the sampling frequency. The factors stored in memory that are a function of the noise estimate are pre-programmed as a function of the number of transitions in the sampled bits for each data bit. For example, if there are eight samples for each data bit and there are zero, one or two transitions in the binary values of the eight bits, the data bit which caused derivation of the samples is considered to have a relatively low noise value, with corresponding values for the quality, eraser and sync indicator bits derived from the address of the memory which was read out in response to the sampled bits. The values of the three bits controlling the data bit sampling rate by the shift register are also a function of the number of transitions of each address of the memory.
A problem with the prior art is that manufacturing tolerances cause different receivers to have a tendency to derive bi-level outputs having slightly different voltage values. For example, if the input to a hard limiter that supplies data pulses to the shift register is nominally between 0 and +5 volts, the input voltage to the hard limiter generally differs from receiver to receiver, by .+-.0.1 volt from the 5 volt level. In the presence of noise, this variation has a tendency to offset the bi-level signal supplied by the hard limiter to the shift register. In consequence, the sampled values derived by the shift register and supplied as address inputs to the memory have a tendency to be biased in a particular receiver. This bias tendency has a particularly adverse impact on the ability of the prior art receivers to accurately detect whether data are present in the signal received by the receiver.
It is, accordingly, an object of the present invention to provide a new and improved receiver for controlling synchronization between the receiver and a received signal, wherein synchronization is achieved in the presence of relatively high noise levels.
Another object of the invention is to provide a new and improved apparatus for and method of synchronizing a receiver to a signal wherein synchronization between the receiver and the signal are provided, as well as an accurate indication of data being present in the received signal.
Another object of the present invention is to provide a new and improved data bit receiver wherein relatively small variations in output signal levels of different receivers do not adversely affect the ability of the receivers to accurately indicate the presence of data in the received signal.